Other Significant Features
- SEC cartridge packaging, developed by Intel, enables high-volume
availability, improved handling protection, and a common form factor
for future high-performance processors.
- High-performance Dual Independent Bus (DIB) architecture (system
bus and cache bus) for high bandwidth, performance and scalability
with future system technologies.
- The system bus supports multiple outstanding transactions to increase
bandwidth availability. It also provides “glueless” support for up to two
processors. This enables low-cost, two-way symmetric multiprocessing,
providing a significant performance boost for multitasking operating
systems and multi-threaded applications.
- A 512K unified, non-blocking, level-two cache that improves performance
by reducing the average memory access time and providing fast
access to recently used instructions and data. Performance is enhanced
through a dedicated 64-bit cache bus. The speed of the level-two cache
scales with the processor core frequency. With a core frequency of 400MHz, the level-two cache bus runs at 200MHzmore than twice the
speed of the Pentium® processor with MMX technology cache access.
This processor also incorporates separate 16K level-one caches, one
for instructions and one for data.
- Supports memory cacheability for up to 4GB of addressable
memory space.
- Available with ECC (Error Correction Code) functionality on the
level-two cache bus for applications where data intensity and reliability
are essential.
- A pipelined Floating-Point Unit (FPU) for supporting the 32-bit
and 64-bit formats specified in IEEE standard 754, as well as an
80-bit format.
- Parity-protected address/request and response system bus signals with
a retry mechanism for high data integrity and reliability.
Testing and Performance Monitoring Features
- Built-in Self Test (BIST) provides single stuck-at fault coverage of the
microcode and large logic arrays, as well as testing of the instruction
cache, data cache, Translation Lookaside Buffers (TLBs) and ROMs.
- IEEE 1149.1 Standard Test Access Port and Boundary Scan mechanism
enables testing of the Pentium II processor and system connections
through a standard interface.
- Internal performance counters for performance monitoring and
event counting.
- Incorporates an on-die diode that can be used to monitor the die
temperature. A thermal sensor located on the motherboard can monitor
the die temperature of the Pentium II processor for thermal management
purposes.
Performance Specifications
NOTES:
- SPECint95, SPECfp95, Norton SI-32 and CPUmark32.
Intel Media Benchmark and Norton Multimedia Benchmark.
Non-ECC level-two cache.